Sequential elements known as monotizers are used in high performance digital designs to enable the correct transition of computation, for example, from a conventional complementary metal-oxide-semiconductor (CMOS) logic stage to a dynamic logic state. The monotizer ensures that the logic state at the input of the monotizer is latched in a race-free manner, and the output of the monotizer, which typically feeds into an input of a dynamic logic, is held in a particular state (depending on the nature of the dynamic logic) so as to ensure robust, glitch-free operation during the evaluation phase of the logic.
FIG. 1 shows a conventional monotizer. While the clock 102 is high, the latch 104 samples the data input, and the outputs, (q_AR and q_ARX), are both held low. As the clock 102 transitions to low, data is latched, and the data and its complementary value are output on q_AR and q_ARX, respectively. As the clock 102 subsequently transitions to high, the latch is free to sample data, and q_AR and q_ARX revert to the logic state 0. Such an implementation incurs a significant delay and degrades the performance.
FIG. 2 shows a conventional monotizer used with a multiplexer. A multiplexer 204 outputs one of the inputs, S1X and S0X, depending on the multiplexer select signal C, and the output of the multiplexer 204 is provided to a latch 206, which latches its input on the falling edge of the clock signal 202. While the clock 202 is high, the outputs Q and Q are both held low. As the clock 202 transitions to low, the output of the multiplexer 204 is latched, and the multiplexer output and its complementary value are output on Q and Q, respectively. As the clock 202 subsequently transitions to high, the latch 206 is free to sample the output of the multiplexer 204, and Q and Q revert to the logic state 0. This implementation incurs a significant delay and degrades the performance.